For illustration, a static random access memory (SRAM) cell includes a pair of bit lines BL and BLB. A low and a high logical value are applied to corresponding bit lines BL and BLB to be written to the memory cell. In various situations, a negative bit line technique is used. For example, a negative voltage value such as a voltage value lower than a value of reference supply voltage VSS is applied to bit line BL. In some conditions, when an absolute value of the voltage on bit line BL increases beyond a certain value, a transistor used to generate the negative voltage for bit line BL breaks down.
Like reference symbols in the various drawings indicate like elements.